US 12,444,449 B2
Output block for array of non-volatile memory cells
Hieu Van Tran, San Jose, CA (US); Hoa Vu, Milpitas, CA (US); Stephen Trinh, San Jose, CA (US); Stanley Hong, San Jose, CA (US); Thuan Vu, San Jose, CA (US); Nghia Le, Ho Chi Minh (VN); Duc Nguyen, Ho Chi Minh (VN); and Hien Pham, Ho Chi Minh (VN)
Assigned to Silicon Storage Technology, Inc., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on May 9, 2023, as Appl. No. 18/195,322.
Claims priority of provisional application 63/446,210, filed on Feb. 16, 2023.
Prior Publication US 2024/0282351 A1, Aug. 22, 2024
Int. Cl. G11C 7/12 (2006.01); G11C 7/14 (2006.01); G11C 7/16 (2006.01); G11C 11/54 (2006.01); G11C 16/26 (2006.01)
CPC G11C 7/16 (2013.01) [G11C 7/12 (2013.01); G11C 7/14 (2013.01); G11C 11/54 (2013.01); G11C 16/26 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells;
an output block coupled to the array, the output block comprising:
a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and
an analog-to-digital converter to convert a voltage received on a first input into a set of output bits;
a first switch to apply, when closed, the first voltage to the first input of the analog-to-digital converter; and
a second switch to apply, when closed, the second voltage to the first input of the analog-to-digital converter.