US 12,444,448 B2
Memory device with memory array connected to circuits in different stacked substrates
Tsuneo Uenaka, Yokkaichi Mie (JP); Tomoya Inden, Yokkaichi Mie (JP); and Shigehiro Yamakita, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 6, 2023, as Appl. No. 18/179,265.
Claims priority of application No. 2022-100918 (JP), filed on Jun. 23, 2022; and application No. 2022-198049 (JP), filed on Dec. 12, 2022.
Prior Publication US 2023/0420007 A1, Dec. 28, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/06 (2006.01); G11C 7/18 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/06 (2013.01); G11C 7/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first silicon substrate on which a first CMOS circuit is formed;
a second silicon substrate on which a second CMOS circuit is formed, the second silicon substrate being above the first silicon substrate in a stacking direction; and
a first memory cell array above the second silicon substrate in the stacking direction, connected to the first CMOS circuit and the second CMOS circuit, and including a plurality of memory cells arranged in the stacking direction, wherein
the second silicon substrate is between the first silicon substrate and the first memory cell array,
the first memory cell array is not between the first and second silicon substrates in the stacking direction,
the first silicon substrate has a first surface and a second surface opposite the first surface,
the first CMOS circuit is formed on the first surface,
the second silicon substrate has a third surface and a fourth surface opposite the fourth surface,
the second CMOS circuit is formed on the third surface, and
the first surface and the fourth surface face each other.