US 12,444,447 B2
Digital phase change memory (PCM) array for analog computing
Tian Shen, Clifton Park, NY (US); Kevin W. Brew, Niskayuna, NY (US); and Heng Wu, Guilderland, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 29, 2021, as Appl. No. 17/565,137.
Prior Publication US 2023/0206964 A1, Jun. 29, 2023
Int. Cl. G11C 7/10 (2006.01); G06F 17/16 (2006.01); G11C 7/12 (2006.01); G11C 7/16 (2006.01); G11C 8/08 (2006.01)
CPC G11C 7/1012 (2013.01) [G06F 17/16 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 7/12 (2013.01); G11C 7/16 (2013.01); G11C 8/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic circuit for multiplying an input vector by a matrix to obtain an output vector, the electronic circuit comprising:
a plurality of bit lines corresponding to elements of said input vector;
a plurality of word lines intersecting said plurality of bit lines at a plurality of grid points;
a plurality of memristive cells located at said plurality of grid points, wherein, for each given one of said bit lines, groups of at least three of said memristive cells are grouped together so that each of said groups represents a single element in the matrix, and wherein said word lines are grouped into corresponding groups of at least three word lines for each element of said output vector;
an analog-to-digital converter coupled to each of said word lines;
for each of said word lines, except a first one of said word lines, in each of said groups of at least three word lines, a shifter having an input coupled to a corresponding one of said analog-to-digital converters and having an output;
for each of said groups of at least three word lines, an addition-subtraction block configured to add said output of said analog-to-digital converter coupled to said first one of said word lines to said outputs of each of said shifters except for said shifter for a last one of said word lines, to subtract said output of said shifter for said last one of said word lines, and to output a result as a corresponding element of said output vector.