US 12,444,446 B2
Dynamic sensing levels for nonvolatile memory devices
Shivananda Shetty, Fremont, CA (US); Yoram Betser, Mazkeret-Batya (IL); Pawan Singh, Cupertino, CA (US); Stefano Amato, Sunnyvale, CA (US); and Alexander Kushnarenko, Haifa (IL)
Assigned to Infineon Technologies LLC, San Jose, CA (US)
Filed by Infineon Technologies LLC, San Jose, CA (US)
Filed on Apr. 22, 2024, as Appl. No. 18/642,283.
Application 18/642,283 is a continuation of application No. 17/649,326, filed on Jan. 28, 2022, granted, now 11,978,528.
Claims priority of provisional application 63/256,126, filed on Oct. 15, 2021.
Prior Publication US 2024/0355368 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/28 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/062 (2013.01) [G11C 7/1048 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array including nonvolatile memory (NVM) cells coupled by a plurality of bit lines, the NVM cells configured to store one of data values or reference values, wherein multiple bit lines of the plurality of bit lines are each coupled to an NVM cell pair storing the reference values;
switching circuitry coupled to the multiple bit lines each coupled to the NVM cell pair, wherein the switching circuitry is configured to select at least one of the NVM cell pairs and output an average reference value of the reference values stored in the selected NVM cell pairs; and
comparator circuitry including one input coupled to a selected NVM cell storing a data value, another input coupled to the switching circuitry, wherein the comparator circuitry is configured to determine a state of the selected NVM cell based on a comparison of the data value stored and the average reference value.