US 12,444,444 B2
Multi-write read-only memory array
Yu-Ting Huang, Hsin-Chu County (TW); and Chi-Pei Wu, Hsin-Chu County (TW)
Assigned to Yield Microelectronics Corp., Hsin-chu County (TW)
Filed by YIELD MICROELECTRONICS CORP., Hsin-Chu County (TW)
Filed on Dec. 5, 2023, as Appl. No. 18/529,115.
Claims priority of application No. 112137822 (TW), filed on Oct. 3, 2023.
Prior Publication US 2025/0111868 A1, Apr. 3, 2025
Int. Cl. G11C 16/04 (2006.01); G11C 5/06 (2006.01); G11C 16/14 (2006.01)
CPC G11C 5/063 (2013.01) [G11C 16/14 (2013.01); G11C 16/0416 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A multi-write read-only memory array comprising:
a plurality of word common-source lines, arranged in parallel, comprising a first word common-source line and a second word common-source line;
a plurality of bit lines arranged in parallel, wherein the plurality of bit lines perpendicular to the plurality of word common-source lines comprise a first bit line and a second bit line; and
a plurality of sub-memory arrays each coupled to two of the plurality of word common-source lines and two of the plurality of bit lines, wherein each of the plurality of sub-memory arrays comprises:
a first memory cell coupled to the first word common-source line and the first bit line;
a second memory cell coupled to the first word common-source line and the second bit line;
a third memory cell coupled to the second word common-source line and the second bit line; and
a fourth memory cell coupled to the second word common-source line and the first bit line.