US 12,444,384 B2
Display substrate and display device of improved wiring
Wei Feng, Beijing (CN); and Xiaofang Gu, Beijing (CN)
Assigned to Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/681,543
Filed by Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 20, 2022, PCT No. PCT/CN2022/120045
§ 371(c)(1), (2) Date Feb. 6, 2024,
PCT Pub. No. WO2023/124279, PCT Pub. Date Jul. 6, 2023.
Claims priority of application No. 202111648000.9 (CN), filed on Dec. 30, 2021.
Prior Publication US 2025/0131895 A1, Apr. 24, 2025
Int. Cl. G09G 3/30 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01)
CPC G09G 3/3677 (2013.01) [G02F 1/136204 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a base substrate, comprising a display region and a bezel region located on at least one side of the display region;
a shift register, located in the bezel region and comprising an output transistor, wherein a first electrode of the output transistor is an output end of the shift register;
a patch panel, located between the shift register and the display region and comprising a first sub patch panel, wherein the first sub patch panel is arranged on a layer same as a layer where a gate of the output transistor is;
a common electrode wire, located between the shift register and the display region, wherein a gap exists between the common electrode wire and the patch panel; and
a jumper, located in the bezel region and comprising a first sub jumper and a second sub jumper, wherein the first sub jumper is located on a side, away from the base substrate, of a layer where the output transistor is, and the second sub jumper is arranged on a layer different from a layer where the first sub patch panel is; and an orthographic projection of the first sub jumper on the base substrate and an orthographic projection of the first sub patch panel on the base substrate overlap each other, an orthographic projection of the second sub jumper on the base substrate and an orthographic projection of the gap on the base substrate do not overlap each other, the first sub jumper connects the first sub patch panel and the second sub jumper, and the second sub jumper is connected to the first electrode of the output transistor.