| CPC G09G 3/3659 (2013.01) [G09G 2310/08 (2013.01)] | 20 Claims |
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7. A data bus, comprising:
a first portion comprising a first slice and a second slice, the first portion configured to receive first image data from a timing controller in a first direction; and
first control circuitry coupled to the first slice and the second slice, the first control circuitry configured to ungate the first slice and the second slice sequentially as the first image data is directly transferred from the first slice to the second slice.
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