US 12,444,381 B2
Method for driving display panel that during a blanking time phase loads a compensation voltage to each data line, display drive circuit, and display device
Yuhang Tian, Beijing (CN); Yanping Liao, Beijing (CN); Dongchuan Chen, Beijing (CN); Shulin Yao, Beijing (CN); Yingmeng Miao, Beijing (CN); Yinlong Zhang, Beijing (CN); Pengfei Hu, Beijing (CN); Wenpeng Ma, Beijing (CN); Zheng Zhang, Beijing (CN); and Jiantao Liu, Beijing (CN)
Assigned to Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/292,812
Filed by Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 29, 2021, PCT No. PCT/CN2021/121618
§ 371(c)(1), (2) Date Jan. 26, 2024,
PCT Pub. No. WO2023/050127, PCT Pub. Date Apr. 6, 2023.
Prior Publication US 2024/0363084 A1, Oct. 31, 2024
Int. Cl. G09G 3/36 (2006.01)
CPC G09G 3/3607 (2013.01) [G09G 3/3614 (2013.01); G09G 2310/08 (2013.01); G09G 2320/02 (2013.01); G09G 2340/0435 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for driving a display panel, wherein
the display panel works in a plurality of continuous display frames, and each display frame comprises a data refresh phase and a blanking time phase; and
the method comprises:
in the data refresh phase of at least one of the plurality of continuous display frames, loading a gate-on voltage to a gate line in the display panel, and loading a data voltage of a to-be-displayed image to each data line, to input a corresponding data voltage to each sub-pixel; and
in the blanking time phase of the at least one of the plurality of continuous display frames, loading a gate-off voltage to the gate line in the display panel, and loading a compensation voltage to each data line;
wherein when the data voltage in the sub-pixel connected with the data line is greater than a common electrode voltage, the compensation voltage loaded on the data line is lower than the data voltage in the sub-pixel connected with the data line; and/or
when the data voltage in the sub-pixel connected with the data line is lower than a common electrode voltage, the compensation voltage loaded on the data line is greater than the data voltage in the sub-pixel connected with the data line;
wherein the display frame, in which the compensation voltage is loaded to each data line in the blanking time phase, is defined as a set display frame;
part of the plurality of continuous display frames are set display frames;
display frames other than the set display frames among the plurality of continuous display frames are non-set display frames;
the non-set display frames comprise:
in the data refresh phase, loading the gate-on voltage to the gate line in the display panel, and loading the data voltage of the to-be-displayed image to each data line, to input the corresponding data voltage to each sub-pixel; and
in the blanking time phase, loading the gate-off voltage to the gate line in the display panel, to enable each data line to be in a suspension joint state.