US 12,444,369 B2
Display substrate
Jie Dai, Beijing (CN); Pengfei Yu, Beijing (CN); Shun Zhang, Beijing (CN); Lu Bai, Beijing (CN); Siyu Wang, Beijing (CN); Mengqi Wang, Beijing (CN); and Hao Zhang, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Apr. 7, 2023, as Appl. No. 18/297,294.
Application 18/297,294 is a continuation of application No. 17/256,563, granted, now 11,699,397, previously published as PCT/CN2020/079482, filed on Mar. 16, 2020.
Prior Publication US 2023/0245623 A1, Aug. 3, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3266 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display substrate, comprising a scan driving circuit and a display area provided on a base substrate, the scan driving circuit comprising a plurality of shift register units and further comprising a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line, all of which extend in a first direction, and the display area comprising at least one driving transistor configured to drive a light-emitting element for display;
wherein at least one of the plurality of shift register units comprises an output circuit and a signal output line, wherein the output circuit is coupled to the first voltage signal line, the second voltage signal line, and the signal output line, and the signal output line extends in a second direction intersecting the first direction;
wherein an orthogonal projection of one or more transistors included in the output circuit on the base substrate is provided between an orthogonal projection of the first voltage signal line on the base substrate and an orthogonal projection of the second voltage signal line on the base substrate;
wherein the at least one of the plurality of shift register units further comprises an output capacitor, a first transistor, a first node control transistor, a second node control transistor, and a third node control transistor;
wherein one of a source electrode and a drain electrode of the first transistor is coupled to one of a first plate and a second plate of the output capacitor, the other of the source electrode and the drain electrode of the first transistor is coupled to the first voltage signal line that is configured to always provide a high-level signal, and a gate electrode of the first transistor is directly coupled to one of a source electrode and a drain electrode of the third node control transistor;
wherein the other plate of the first plate and the second plate of the output capacitor is directly coupled to the first voltage signal line;
wherein the at least one shift register unit further comprises a second capacitor connecting transistor;
wherein one of a source electrode and a drain electrode of the second node control transistor and one of a source electrode and a drain electrode of the first node control transistor are coupled through a fourth conductive connection portion;
wherein the at least one shift register unit further comprises a fifth conductive connection portion coupled to a gate electrode of the second capacitor connecting transistor, and an orthogonal projection of the fifth conductive connection portion on the base substrate has a seventh overlap area with an orthogonal projection of the fourth conductive connection portion on the base substrate; and
wherein the fifth conductive connection portion is coupled to the fourth conductive connection portion through a seventh via hole provided in the seventh overlap area.