| CPC G09G 3/3233 (2013.01) [G09G 2300/0465 (2013.01); G09G 2300/0819 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01)] | 20 Claims |

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1. A display substrate, comprising:
a base substrate;
a plurality of sub-pixels provided on the base substrate, wherein the plurality of sub-pixels are arranged in a first direction and a second direction, and comprise a light emitting element;
a plurality of pixel driving circuits provided on the base substrate, wherein the plurality of pixel driving circuits are arranged in the first direction and the second direction, the plurality of pixel driving circuits are configured to drive the light emitting elements of the plurality of sub-pixels respectively, and at least one pixel driving circuit comprises at least two transistors;
an initialization voltage signal line provided on the base substrate, wherein the initialization voltage signal line comprises a portion extending in the first direction, and the initialization voltage signal line is configured to provide an initialization voltage signal to the at least one pixel driving circuit; and
a control signal line provided on the base substrate, wherein the control signal line comprises a portion extending in the first direction, and the control signal line is configured to provide a control signal to the at least one pixel driving circuit so as to control the at least two transistors of the at least one pixel driving circuit to turn on,
wherein in a frame of driving the pixel driving circuits of a row of sub-pixels, the control signal on the control signal line controls the at least two transistors of the at least one pixel driving circuit to turn on in at least one first time period, and the initialization voltage signal on the initialization voltage signal line is provided to the at least one pixel driving circuit in a second time period, wherein the first time period is separated from the second time period in timing; and
the initialization voltage signal line and the control signal line are located in different conductive layers, an orthographic projection of the initialization voltage signal line on the base substrate overlaps at least partially with an orthographic projection of the control signal line on the base substrate, and in at least one of the sub-pixels, a ratio of an area of an overlapping portion to an area of the orthographic projection of the control signal line on the base substrate is in a range from 60% to 100%.
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