US 12,444,359 B2
Display apparatus operated with low refresh rate and method of driving the same
Nam-Kil Park, Paju-si (KR); and Jung-Min Lee, Paju-si (KR)
Assigned to LG Display Co., Ltd., Seoul (KR)
Filed by LG Display Co., Ltd., Seoul (KR)
Filed on Jan. 16, 2024, as Appl. No. 18/414,134.
Claims priority of application No. 10-2023-0012455 (KR), filed on Jan. 31, 2023.
Prior Publication US 2024/0257737 A1, Aug. 1, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/20 (2006.01); H10K 59/131 (2023.01)
CPC G09G 3/3233 (2013.01) [G09G 3/2092 (2013.01); H10K 59/131 (2023.02); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0857 (2013.01); G09G 2320/043 (2013.01); G09G 2340/0435 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A display device, comprising:
a timing controlling circuit configured to generate an image data, a data control signal and a gate control signal;
a data driving circuit configured to generate a data signal using the image data and the data control signal;
a gate driving circuit configured to generate a gate signal using the gate control signal; and
a display panel configured to display an image using the data signal and the gate signal,
wherein a start signal of the gate control signal has one pulse between a logic high voltage and a logic low voltage during a refresh subframe where the data signal and the gate signal are supplied, and the start signal of the gate control signal has a plurality of pulses between the logic high voltage and the logic low voltage during an anode reset subframe where supply of the data signal and the gate signal is stopped, and
wherein a clock of the gate control signal has a plurality of pulses between the logic high voltage and the logic low voltage during the refresh subframe, and the clock of the gate control signal has the logic high voltage during the anode reset subframe.