US 12,444,356 B2
Display substrate, manufacturing method thereof and display apparatus
Ning Cong, Beijing (CN); Longfei Fan, Beijing (CN); Dachao Li, Beijing (CN); Can Zhang, Beijing (CN); Minghua Xuan, Beijing (CN); and Xiaochuan Chen, Beijing (CN)
Assigned to Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/267,788
Filed by BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jul. 29, 2022, PCT No. PCT/CN2022/108886
§ 371(c)(1), (2) Date Jun. 16, 2023,
PCT Pub. No. WO2024/021001, PCT Pub. Date Feb. 1, 2024.
Prior Publication US 2024/0395200 A1, Nov. 28, 2024
Int. Cl. G09G 3/3233 (2016.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC G09G 3/3233 (2013.01) [H10K 59/1201 (2023.02); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/1315 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising a display area and a border area,
wherein the display area comprises a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns,
a sub-pixel comprises a first region, a gap region and a second region arranged in sequence along a pixel row direction;
at least one sub-pixel comprises a pixel driving circuit, a first scan signal line and a second scan signal line,
the pixel driving circuit at least comprises a first transistor, a second transistor and a third transistor,
the first scan signal line is configured to control turning-on or turning-off of the first transistor, and the second scan signal line is configured to control turning-on or turning-off of the second transistor;
the first transistor at least comprises a first gate electrode, a first active layer, a first electrode and a second electrode of the first transistor, the second transistor at least comprises a second gate electrode and a second active layer, and the third transistor at least comprises a third gate electrode and a third active layer;
the first active layer is disposed in the first region, the second active layer and the third active layer are disposed in the second region, and the second active layer is disposed in a plane at one side of the third active layer in a pixel column direction;
the first scan signal line is connected to the first gate electrode through a first gate via hole, the second electrode of the first transistor is connected to the second gate electrode through a second gate via hole, the second scan signal line is connected to the third gate electrode through a third gate via hole, and the first gate via hole, the second gate via hole and the third gate via hole are provided in the gap region.