| CPC G09G 3/3233 (2013.01) [G09G 3/32 (2013.01); G09G 2300/0842 (2013.01); G09G 2320/0233 (2013.01); H10K 59/00 (2023.02)] | 12 Claims |
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1. A display substrate, comprising:
a base substrate, comprising a display area and a border area arranged outside the display area, wherein the display area comprises: a first display area, and a second display area at least arranged on a side of the first display area;
a plurality of light emitting devices, arranged on the base substrate in an array, wherein the plurality of light emitting devices comprise: a plurality of first light emitting devices in the first display area, and a plurality of second light emitting devices in the second display area;
a plurality of pixel driving circuits, arranged between the base substrate and the light emitting devices, wherein the plurality of pixel driving circuits comprise: a plurality of first pixel driving circuits and a plurality of second pixel driving circuits, the plurality of first pixel driving circuits and the plurality of first light emitting devices are correspondingly electrically connected, the plurality of second pixel driving circuits at least partially overlap with the plurality of second light emitting devices, and the plurality of second pixel driving circuits are correspondingly electrically connected with the plurality of second light emitting devices, at least one of the plurality of second pixel driving circuits is provided with a driving transistor, a threshold compensation transistor, and a gate connection electrode, and the gate connection electrode is electrically connected with a gate electrode of the driving transistor and a source electrode of the threshold compensation transistor, or the gate connection electrode is electrically connected with a gate electrode of the driving transistor and a drain electrode of the threshold compensation transistor; and
a plurality of connection leads, wherein each of at least part of the connection leads is electrically connected with at least one first pixel driving circuit and one first light emitting device, and orthographic projections of the connection leads on the base substrate do not overlap an orthographic projection of the gate connection electrode on the base substrate;
wherein the second display area comprises a plurality of pixel driving circuit columns arranged in a first direction, and the plurality of pixel driving circuit columns comprise: a plurality of first pixel driving circuit columns and a plurality of second pixel driving circuit columns;
the first pixel driving circuit columns only comprise the plurality of first pixel driving circuits arranged in a second direction, and the first direction intersects with the second direction;
the second pixel driving circuit columns comprise: the plurality of first pixel driving circuits arranged in the second direction, and the second pixel driving circuits located between at least part of adjacent first pixel driving circuits in the second direction;
the first display area comprises a plurality of first light emitting device columns arranged in the first direction, and each of the plurality of first light emitting device columns comprises the plurality of first light emitting devices arranged in the second direction; and
each first light emitting device in each of the plurality of first light emitting device columns is electrically connected with at least part of the first pixel driving circuits in one corresponding first pixel driving circuit column respectively;
wherein at least one of the plurality of connection leads comprises: a first lead portion extending in the second direction, a second lead portion extending in the second direction, and a third lead portion extending in the first direction and electrically connected with the first lead portion and the second lead portion;
the first lead portion is led out from the first pixel driving circuit columns and electrically connected with at least part of the first pixel driving circuits in the first pixel driving circuit columns;
the second lead portion is led out from the first light emitting device columns and electrically connected with the first light emitting devices in the first light emitting device columns;
an orthographic projection of the third lead portion on the base substrate does not overlap the first display area and the second display area; or,
at least part of the orthographic projection of the third lead portion on the base substrate does not overlap the first display area and the second display area, and a rest part of the orthographic projection of the third lead portion on the base substrate has overlapping areas with the first display area and the second display area;
wherein the plurality of connection leads comprise: first connection leads, arranged between the pixel driving circuits and the light emitting devices;
the first connection leads comprise a plurality of layers of connection sub leads located in different film layers; and
the connection sub leads located in different film layers are electrically connected with different first pixel driving circuits and first light emitting devices respectively, and the connection sub leads located in different film layers are not connected with each other;
wherein all the orthographic projections of the plurality of layers of connection sub leads on the base substrate do not overlap with each other;
at least one of the light emitting devices comprises: an anode, light emitting functional layers, and a cathode, and the anode, the light emitting functional layers, and the cathode are arranged sequentially in a stacked mode; and
the connection leads further comprise:
second connection leads, arranged in a same layer as the anode, wherein the second connection leads are electrically connected with the first connection leads.
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