US 12,444,354 B2
Array substrate and display apparatus
Quanyong Gu, Beijing (CN); Tiaomei Zhang, Beijing (CN); Mengqi Wang, Beijing (CN); De Li, Beijing (CN); Hong Yi, Beijing (CN); Zhongliu Yang, Beijing (CN); and Zhengkun Li, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/004,892
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jan. 4, 2022, PCT No. PCT/CN2022/070043
§ 371(c)(1), (2) Date Jan. 10, 2023,
PCT Pub. No. WO2023/130202, PCT Pub. Date Jul. 13, 2023.
Prior Publication US 2025/0273138 A1, Aug. 28, 2025
Int. Cl. G09G 3/3233 (2016.01); G09G 3/32 (2016.01); H10D 86/40 (2025.01)
CPC G09G 3/3233 (2013.01) [G09G 3/32 (2013.01); H10D 86/441 (2025.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising a base substrate, and a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels;
wherein a respective pixel driving circuit comprises:
a driving transistor;
a compensation transistor configured to provide a compensation voltage signal to a gate electrode of the driving transistor; the compensation transistor comprising a source electrode, a drain electrode and a gate electrode;
a node connecting line in a first signal line layer;
a first pad in a second signal line layer on a side of the first signal line layer away from the base substrate;
a voltage line configured to output a constant voltage signal; and
a voltage connecting line electrically connecting the first pad with the voltage line;
wherein the node connecting line connects the gate electrode of the driving transistor and a drain electrode of the compensation transistor;
an orthographic projection of the first pad on a base substrate at least partially overlaps with an orthographic projection of the node connecting line on the base substrate; and
an orthographic projection of the voltage line and the voltage connecting line on the base substrate is spaced apart from the orthographic projection of the node connecting line on the base substrate.