| CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G09G 3/3283 (2013.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02); G09G 2300/0417 (2013.01); G09G 2300/043 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0262 (2013.01); G09G 2320/0238 (2013.01); G09G 2330/023 (2013.01); H10D 30/6745 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01)] | 13 Claims |
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1. An organic light emitting diode display device comprising:
a plurality of pixels;
a plurality of scan lines connected to the plurality of pixels and which transmits corresponding scan signals to the plurality of pixels;
a plurality of a second lines connected to the plurality of pixels and which transmits corresponding a second signal to the plurality of pixels; and
a plurality of data lines connected to the plurality of pixels and which transmits corresponding data signals to the plurality of pixels,
wherein at least one of the plurality of pixels includes:
an organic light emitting diode connected between a first power supply and a second power supply;
a first transistor connected in series with the organic light emitting diode between the first power supply and the second power supply;
a second transistor turned on by a scan signal received from a corresponding one of the plurality of scan lines which transmits a data signal received from a corresponding one of the plurality of data lines to one electrode of the first transistor;
a capacitor connected to a gate electrode of the first transistor and stores a voltage corresponding to the data signal;
a third transistor interposed between the organic light emitting diode and the first transistor;
a fourth transistor turned on by the scan signal applying an initialization voltage to the anode of the organic light emitting diode;
a fifth transistor turned on by the scan signal which compensates a threshold voltage of the first transistor and is connected to the first transistor;
a sixth transistor interposed between the first transistor and the first power supply and turned on by the second signal; and
a seventh transistor turned on by an initialization signal enabled at a timing different from the scan signal, which applies an initialization voltage to the gate electrode of the first transistor,
wherein a gate electrode of the fourth transistor is connected to a first scan line which supplies the scan signal, while a gate electrode of the seventh transistor is connected to a second scan line different from the first scan line, the second scan line supplies the initialization signal different from the scan signal,
wherein the scan signal supplied to the gate electrode of the fourth transistor is configured to have a high voltage only during a first time period that extends from a first time to a second time,
wherein the initialization signal supplied to the gate electrode of the seventh transistor is configured to have a high voltage only during a second time period, which extends from the second time to a third time,
wherein the first transistor and the third transistor, are p-type transistors and the fifth transistor, the sixth transistor, and the seventh transistor are n-type transistors; and
wherein the first transistor and the third transistor, are polycrystalline silicon semiconductor transistors, and the fifth transistor, the sixth transistor, and the seventh transistor are oxide semiconductor transistors.
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