US 12,444,340 B2
Display panel, driving method thereof, and display device
Yingteng Zhai, Xiamen (CN)
Assigned to Tianma Advanced Display Technology Institute (Xiamen) Co., Ltd., Xiamen (CN)
Filed by Tianma Advanced Display Technology Institute (Xiamen) Co., Ltd., Xiamen (CN)
Filed on Mar. 12, 2024, as Appl. No. 18/602,092.
Claims priority of application No. 202311439539.2 (CN), filed on Oct. 31, 2023.
Prior Publication US 2024/0212561 A1, Jun. 27, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/20 (2006.01); G09G 3/32 (2016.01)
CPC G09G 3/2081 (2013.01) [G09G 3/2011 (2013.01); G09G 3/2014 (2013.01); G09G 3/32 (2013.01); G09G 3/3233 (2013.01); G09G 2300/0819 (2013.01); G09G 2310/062 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0633 (2013.01); G09G 2320/064 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display panel, comprising pixel circuits and light-emitting elements, wherein
a pixel circuit among the pixel circuits comprises an amplitude modulation circuit and a pulse width modulation circuit;
the amplitude modulation circuit comprises an amplitude driving sub-module and an amplitude reset sub-module, wherein the amplitude reset sub-module is configured to transmit a first reset signal to a control terminal of the amplitude driving sub-module;
the pulse width modulation circuit comprises a pulse width driving sub-module and a pulse width reset sub-module, wherein the pulse width reset sub-module is configured to transmit a second reset signal to a control terminal of the pulse width driving sub-module; and
a voltage value of the first reset signal is Vref1, and a voltage value of the second reset signal is Vref2; wherein
the amplitude modulation circuit comprises an amplitude data write sub-module configured to transmit a first data signal to the amplitude driving sub-module;
the pulse width modulation circuit comprises a pulse width data write sub-module configured to transmit a second data signal to the pulse width driving sub-module; and
a voltage value of the first data signal is Vdata1, a voltage value of the second data signal is Vdata2; and wherein Vdata1<Vdata2, Vref1<Vref2;
wherein the amplitude reset sub-module is electrically connected to a first reset signal line, and the pulse width reset sub-module is electrically connected to a second reset signal line; and the first reset signal line is configured to transmit the first reset signal, and the second reset signal line is configured to transmit the second reset signal; and
wherein the amplitude modulation circuit comprises an amplitude data write sub-module connected to a first data line;
the pulse width modulation circuit comprises a pulse width data write sub-module connected to a second data line; and
a control terminal of the amplitude data write sub-module and a control terminal of the pulse width data write sub-module are electrically connected to a same second scanning line.