US 12,444,120 B2
Rendering system and method based on system-on-chip (SOC) platform
Peng Wan, Nanjing (CN); and Lili Dai, Nanjing (CN)
Assigned to Nanjing SemiDrive Technology LTD., Nanjing (CN)
Filed by Nanjing SemiDrive Technology LTD., Nanjing (CN)
Filed on Jan. 26, 2023, as Appl. No. 18/159,880.
Claims priority of application No. 202210853087.1 (CN), filed on Jul. 20, 2022.
Prior Publication US 2024/0029335 A1, Jan. 25, 2024
Int. Cl. G06T 15/00 (2011.01); G06F 15/173 (2006.01); G06F 15/78 (2006.01)
CPC G06T 15/005 (2013.01) [G06F 15/17325 (2013.01); G06F 15/7814 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A rendering system based on a system-on-chip (SOC) platform comprising:
a plurality of processors divided into a plurality of processor groups, a plurality of operating systems being run by the plurality of processor groups, different processor groups in the plurality of processor groups not sharing an operating system;
a plurality of graphics processors receiving rendering tasks sent by the plurality of operating systems, respectively, the plurality of graphics processors being in a one-to-one correspondence with the plurality of processor groups;
an inter-core communication circuit configured to cause the plurality of processors of the plurality of processor groups to communicate with each other; and
a shared memory, the plurality of graphics processors reading image data in the shared memory, and rendered image data being transmitted to the shared memory;
wherein:
in response to a rendering task being distributed to the plurality of processor groups by the inter-core communication circuit, the plurality of graphics processors corresponding to the plurality of processor groups read the image data corresponding to the rendering task in the shared memory and perform collaborative rendering, and
wherein a processor of one of the plurality of processor groups is configured to:
determine whether the plurality of processors are needed to perform rendering collaboratively;
determine the plurality of graphics processors that perform the rendering collaboratively through the inter-core communication circuit; and
integrate a result after the collaborative rendering and outputting the result,
wherein determining whether the plurality of processors are needed to perform the rendering collaboratively further includes:
determining whether processors of other processor groups of the plurality of processor groups are needed to perform the rendering collaboratively, whether the one of the plurality of processor groups performs the rendering task or the plurality of processor groups perform the rendering task collaboratively being determined according to complexity of a scenario of the rendering task, and
wherein determining the plurality of graphics processors that perform the rendering collaboratively through the inter-core communication circuit further includes:
in response to determining that the collaborative rendering is needed, notifying the processors of the other processor groups of the plurality of processor groups through the inter-core communication circuit, otherwise a graphics processor corresponding to the one of the plurality of processor groups performs the rendering alone;
determining, by the other processor groups, whether a graphics processor corresponding to one of the other processor groups is available; and
in response to determining that the graphics processor corresponding to the one of the other processor groups is available, performing the collaborative rendering by the graphics processor corresponding to the one of the plurality of processor groups and the graphics processor corresponding to the one of the other processor groups, otherwise the graphics processor corresponding to the one of the plurality of processor groups performs the rendering alone.