US 12,443,868 B2
Quantum error mitigation using hardware-friendly probabilistic error correction
Christophe Piveteau, Zürich (CH); David Sutter, Zürich (CH); and Stefan Woerner, Aarau (CH)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 23, 2020, as Appl. No. 17/029,290.
Prior Publication US 2022/0092460 A1, Mar. 24, 2022
Int. Cl. G06N 10/00 (2022.01); G06F 17/18 (2006.01); G06F 18/10 (2023.01); G06N 10/70 (2022.01); H03K 19/20 (2006.01)
CPC G06N 10/00 (2019.01) [G06F 17/18 (2013.01); G06F 18/10 (2023.01); G06N 10/70 (2022.01); H03K 19/20 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A system, comprising:
a quantum processor;
a memory that stores computer executable components; and
a classical processor that executes the computer executable instructions stored in the memory to perform operations comprising:
optimizing probabilistic error mitigation on the quantum processor, wherein the optimizing comprises:
generating an approximate decomposition of a quantum gate into a weighted combination of hardware-implementable quantum channels using quasi-probability coefficients;
determining a total sampling overhead constraint for the quantum circuit based on the decomposition;
distributing a total sampling budget across a plurality of gates in the circuit to minimize cumulative variance introduced by probabilistic sampling;
selecting an optimal set of quantum channels and associated coefficients that approximate a trace-preserving linear transformation of a quantum state, such that the approximation minimizes deviation from an ideal behavior while constraining the magnitude of the coefficients;
generating a unitary realization of the selected quantum channel combination using Stinespring dilation, wherein the realization is optimized via variational approximation subject to a rank constraint based on available ancilla qubit resources; and
controlling the execution of the decomposed and optimized quantum operations on the quantum processor, such that quantum sampling overhead is reduced and circuit fidelity is improved on noisy intermediate-scale quantum hardware.