US 12,443,837 B2
Neural network accelerator in DIMM form factor
Doe Hyun Yoon, Foster City, CA (US); Lifeng Nai, Sunnyvale, CA (US); and Peter Ma, Mountain View, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Aug. 17, 2020, as Appl. No. 16/994,990.
Prior Publication US 2022/0051089 A1, Feb. 17, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/02 (2006.01); G06F 13/40 (2006.01); G06N 3/063 (2023.01); G06N 3/065 (2023.01); G06N 3/08 (2023.01)
CPC G06N 3/065 (2023.01) [G06F 9/30098 (2013.01); G06F 9/3877 (2013.01); G06F 13/4027 (2013.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neural network dual in-line memory module (NN-DIMM), comprising:
a module card having a plurality of parallel edge contacts adjacent an edge of a slot connector thereof and configured to have the same command and signal interface as a standard dual in-line memory module (DIMM);
a deep neural network (DNN) accelerator affixed to the module card; and
a bridge configured to transfer information between the DNN accelerator and the plurality of parallel edge contacts via a DIMM external interface, and
wherein the bridge includes control registers and on-chip memory are accessible as a standard DRAM to a host CPU, wherein the bridge is configured to map the control registers and the on-chip memory to one row of a plurality of banks of the NN-DIMM, and wherein access of the control registers or the on-chip memory is limited to the one row of the plurality of banks.