US 12,443,834 B2
Binary neural network in memory
Dmitry Vengertsev, Boise, ID (US); Seth A. Eichmeyer, Boise, ID (US); Jing Gong, Kirkland, WA (US); John Christopher M. Sancon, Boise, ID (US); Nicola Ciocchini, Boise, ID (US); and Tom Tangelder, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 13, 2021, as Appl. No. 17/319,765.
Prior Publication US 2022/0366224 A1, Nov. 17, 2022
Int. Cl. G06N 3/063 (2023.01); G06N 3/04 (2023.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01)
CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01); G11C 11/54 (2013.01); G11C 13/0004 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an array of memory cells;
a controller coupled to the memory array and configured to:
quantize an original neural network having non-binary elements to generate a first binary neural network including a first plurality of elements each having a value of one or zero;
generate a secondary binary neural network based on the first binary neural network by:
performing a plurality of linear transformations on weights of the first binary neural network to generate a first plurality of vectors;
performing drop out operations on the first plurality of vectors to generate a second plurality of vectors;
performing argmax transformations on at least one of the second plurality of vectors;
wherein the second binary neural network including a second plurality of elements each having a respective non-zero value corresponding to a resistive state storable in a memory cell of the array of memory cells;
store each of the second plurality of elements as a first resistive state or a second resistive state in the array of memory cells; and
execute the second binary neural network on the array by performing vector-matrix multiplication using the resistive states of the memory cells.