US 12,443,832 B1
Neural network architecture with high bandwidth memory (HBM)
Xianpei Zheng, Jr., Beijing (CN); Zhongmin Chen, Beijing (CN); Lingzhi Sui, Beijing (CN); Pengbo Zheng, Beijing (CN); Xiang Feng, Beijing (CN); Chong Sun, Beijing (CN); Yu Zhang, Beijing (CN); and Enshan Yang, Beijing (CN)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Apr. 30, 2021, as Appl. No. 17/245,339.
Int. Cl. G06N 3/063 (2023.01); G06F 13/40 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 13/4022 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a high bandwidth memory (HBM) device comprising random access memory (RAM) distributed over multiple dies that are arranged in a stacked configuration, a first portion of the RAM is configured as virtual banks of RAM dedicated to storing feature map data of a convolutional neural network (CNN) application program, and wherein a second portion of the RAM is dedicated to supporting data exchanges with a host;
a CNN engine comprising:
a convolutional instruction processor configured to execute convolutional layer instructions of the CNN application program; and
a depthwise convolutional instruction processor configured to execute depthwise layer instructions of the CNN application program; and
point-to-point interface circuitry configured to permit the convolutional instruction processor and the depthwise convolutional instruction processor to access respective first and second sets of the virtual banks of the RAM;
wherein the convolutional instruction processor and the depthwise convolutional instruction processor are further configured to write and read feature map data of the CNN application program to and from the respective first and second sets of the virtual banks of RAM via the point-to-point interface circuitry.