US 12,443,783 B2
Logic circuit design method
Le Ye, Zhejiang (CN); Zhixuan Wang, Zhejiang (CN); Qianqian Huang, Zhejiang (CN); Yangyuan Wang, Zhejiang (CN); and Ru Huang, Zhejiang (CN)
Assigned to HANGZHOU WEIMING XINKE TECHNOLOGY CO., LTD, Zhejiang (CN); and ADVANCED INSTITUTE OF INFORMATION TECHNOLOGY (AIIT), PEKING UNIVERSITY, Zhejiang (CN)
Appl. No. 17/786,993
Filed by HANGZHOU WEIMING XINKE TECHNOLOGY CO., LTD, Zhejiang (CN); and ADVANCED INSTITUTE OF INFORMATION TECHNOLOGY (AIIT), PEKING UNIVERSITY, Zhejiang (CN)
PCT Filed Dec. 9, 2020, PCT No. PCT/CN2020/135034
§ 371(c)(1), (2) Date Jun. 17, 2022,
PCT Pub. No. WO2021/121107, PCT Pub. Date Jun. 24, 2021.
Claims priority of application No. 201911305046.3 (CN), filed on Dec. 17, 2019.
Prior Publication US 2023/0030944 A1, Feb. 2, 2023
Int. Cl. G06F 30/398 (2020.01); G06F 119/06 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 2119/06 (2020.01)] 9 Claims
OG exemplary drawing
 
1. A method for designing a logic circuit, comprising:
designing and generating an initial MOSFET-TFET hybrid logic circuit, wherein the MOSFET-TFET hybrid logic circuit comprises several logic gates;
replacing a first type of TFET with a MOSFET in a series branch of the initial MOSFET-TFET hybrid logic circuit, wherein the first type of TFET is directly connected to the ground or to a power supply and is not directly connected to output terminals of the logic gates;
adjusting the logic circuit after the first type of TFET is replaced with the MOSFET to a static standby state;
adjusting a first-level logic gate in the logic circuit in the static standby state to a preset logic input state;
acquiring static input bias state information of all the logic gates;
determining a first type of logic gate according to the static input bias state information, wherein the first type of logic gate is a logic gate whose leakage state is determined by the MOSFET, and wherein the first type of logic gate comprises a NAND gate with a first input state of IN A=0 and IN B=1 or a NOR gate with a second input state of IN A=1 and IN B=0 during the static standby state; and
exchanging correspondingly connected output terminals of at least two input terminals of the first type of logic gate, wherein the correspondingly connected output terminal is an output terminal in an upper-level logic gate that is correspondingly connected with the input terminal.