US 12,443,782 B2
Metal cut region location method
Jung-Chan Yang, Hsinchu (TW); Ting Yu Chen, Hsinchu (TW); Li-Chun Tien, Hsinchu (TW); and Fong-Yuan Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 21, 2023, as Appl. No. 18/304,661.
Application 17/237,484 is a division of application No. 16/580,874, filed on Sep. 24, 2019, granted, now 10,997,348, issued on May 4, 2021.
Application 18/304,661 is a continuation of application No. 17/237,484, filed on Apr. 22, 2021, granted, now 11,636,248.
Claims priority of provisional application 62/738,823, filed on Sep. 28, 2018.
Prior Publication US 2023/0267262 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/392 (2020.01); G06F 30/394 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/394 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of generating an integrated circuit (IC) layout diagram, the method comprising:
positioning a cell in the IC layout diagram relative to a first metal layer cut region alignment pattern; and
overlapping the cell with a first metal layer cut region,
wherein
the cell comprises a first metal layer region corresponding to one of a first or second mask set,
the first metal layer cut region alignment pattern comprises a sub-pattern corresponding to the one of the first or second mask set, and
the first metal layer cut region corresponds to the sub-pattern.