US 12,443,761 B2
Method and system for FPGA-based encrypted VPN
Timur Askerov, Rishon LeZion (IL); and Roman Vercetti, Holon (IL)
Assigned to ENQUANTUM LTD, Holon (IL)
Appl. No. 18/570,420
Filed by ENQUANTUM LTD, Holon (IL)
PCT Filed Jun. 22, 2022, PCT No. PCT/IL2022/050675
§ 371(c)(1), (2) Date Dec. 14, 2023,
PCT Pub. No. WO2022/269615, PCT Pub. Date Dec. 29, 2022.
Claims priority of provisional application 63/213,334, filed on Jun. 22, 2021.
Prior Publication US 2024/0296254 A1, Sep. 5, 2024
Int. Cl. G06F 21/76 (2013.01); G06F 21/60 (2013.01); G06F 21/64 (2013.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01)
CPC G06F 21/76 (2013.01) [G06F 21/602 (2013.01); G06F 21/64 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for encrypted communications, comprising:
receiving at a first field programmable gate array (FPGA) and at a second FPGA, from a master controller, respective encrypted bitstreams of encryption firmware;
decrypting the encrypted bitstreams within the first and second FPGAs and loading the resulting encryption firmware to programmable logic blocks (PLBs) of the first and second FPGAs;
executing at the first FPGA steps of:
receiving an unencrypted data payload;
generating a random seed value;
generating a hash key from parameters that include the random seed value and a value representing an encrypted channel ID (EID) of a network communications channel between the first and second FPGAs, by applying the encryption firmware, wherein a size of the hash key equals is the given size of the unencrypted data payload;
XORing the hash key with the unencrypted data payload to generate an encrypted data payload;
assembling an encrypted data packet including the seed and the encrypted data payload and sending the encrypted data packet to the second FPGA over the network communications channel identified by the EID; and
executing at the second FPGA further steps of:
receiving the encrypted data packet with the seed and the encrypted data payload;
generating the hash key from the parameters including the seed value and the EID value, by applying the encryption firmware;
XORing the hash key with the encrypted data payload to regenerate the unencrypted data payload; and
delivering the unencrypted data payload from the second FPGA to a target address.