US 12,443,657 B2
High bandwidth content addressable memory (CAM) based hardware architecture for datacenter networking
Srinivas Vaduvatha, San Jose, CA (US); and Weihuang Wang, Los Gatos, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/547,334.
Claims priority of provisional application 63/192,626, filed on May 25, 2021.
Prior Publication US 2022/0382783 A1, Dec. 1, 2022
Int. Cl. G06F 16/901 (2019.01); H04L 45/745 (2022.01)
CPC G06F 16/9017 (2019.01) [H04L 45/74591 (2022.05)] 20 Claims
OG exemplary drawing
 
1. A content addressable memory module in a computing system, comprising:
a plurality of sub-content addressable memories logically partitioned from a reorder primary content addressable memory in the computing system;
a plurality of sub-content addressable memories logically partitioned from a retransmission primary content addressable memory in the computing system;
a plurality of searchable first-in first out (FIFO) interfaces configured to be in communication with respective sub-content addressable memories from the plurality of sub-content addressable memories of the reorder primary content addressable memory and the retransmission primary content addressable memory;
one or more processors in communication with the content addressable memory module, the one or more processors configured to:
receive a set of data packets;
perform a lookup operation to access data entries stored in each of the sub-content addressable memories in one of the reorder primary content addressable memory and the retransmission primary content addressable memory; and
perform an update operation at a selected sub-content addressable memory from the plurality of the sub-content addressable memories in one of the reorder primary content addressable memory and the retransmission primary content addressable memory.