US 12,443,558 B2
Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width
Vedvyas Shanbhogue, Austin, TX (US); Stephen J. Robinson, Austin, TX (US); Christopher D. Bryant, Austin, TX (US); and Jason W. Brandt, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 21, 2024, as Appl. No. 18/670,721.
Application 18/670,721 is a continuation of application No. 17/827,882, filed on May 30, 2022, granted, now 12,007,938.
Application 17/827,882 is a continuation of application No. 17/131,729, filed on Dec. 22, 2020, granted, now 11,347,680, issued on May 31, 2022.
Application 17/131,729 is a continuation of application No. 15/089,525, filed on Apr. 2, 2016, granted, now 10,901,940, issued on Jan. 26, 2021.
Prior Publication US 2024/0427728 A1, Dec. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 15/80 (2006.01)
CPC G06F 15/8007 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/30112 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08)] 21 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of caches;
decode circuitry to decode an instruction, the instruction indicating first information to reference a source memory location and second information to reference a destination memory location, wherein the instruction to indicate the second information is to indicate a general-purpose register, the general-purpose register to store relative memory address information to be combined with information from a segment register to address the destination memory location; and
execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, including to:
load 512 bits of data from the source memory location; and
atomically store the 512 bits of data to the destination memory location.