US 12,443,555 B2
Frame alignment recovery for a high-speed signaling interconnect
Seema Kumar, Santa Clara, CA (US); and Ish Chadha, San Jose, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Dec. 13, 2023, as Appl. No. 18/538,758.
Application 18/538,758 is a continuation of application No. 17/556,892, filed on Dec. 20, 2021, granted, now 11,899,609.
Prior Publication US 2024/0111706 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/42 (2006.01); G06F 1/12 (2006.01); H04J 3/06 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01); H04L 7/10 (2006.01); H04L 25/14 (2006.01)
CPC G06F 13/4208 (2013.01) [G06F 1/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A receiver device comprising:
a plurality of data lanes;
per-lane unit interval (UI) shift logic coupled to the plurality of data lanes, wherein each of the plurality of data lanes receives, from a transmitter device, an incoming data stream having a same pattern repeated at a number of clock cycles and the per-lane UI shift logic is to shift the incoming data stream one UI at a time until a shifted data pattern matches an expected data pattern on each data lane; and
per-lane burst length (BL) shift logic coupled to the plurality of data lanes, wherein each of the plurality of data lanes receives, from the transmitter device, a count value at every clock cycle and the per-lane BL shift logic is to shift one or more BLs until each data lane receives a same count value, representing the plurality of data lanes being synchronized with respect to a same frame boundary.