US 12,443,549 B2
Memory system and control method
Haruka Mori, Kawasaki Kanagawa (JP); and Mitsunori Tadokoro, Fujisawa Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 23, 2023, as Appl. No. 18/113,483.
Claims priority of application No. 2022-082335 (JP), filed on May 19, 2022.
Prior Publication US 2023/0376433 A1, Nov. 23, 2023
Int. Cl. G06F 13/16 (2006.01); G06F 13/22 (2006.01)
CPC G06F 13/1673 (2013.01) [G06F 13/1689 (2013.01); G06F 13/22 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory system comprising:
one or more channels;
a first number of memory elements; and
a memory controller that is connected to the first number of memory elements via the one or more channels and includes:
a second number of polling circuits, the second number being smaller than the first number; and
a first processor configured to:
determine one or more polling circuits not executing a polling operation among the second number of polling circuit;
select a polling circuit that is not executing the polling operation among the determined one or more polling circuits; and
designate, for the selected polling circuit, one memory element out of the first number of memory elements and cause the selected polling circuit to execute the polling operation on the designated one memory element, wherein
each of the second number of polling circuits is configured to, in response to the designation by the first processor, execute the polling operation,
the polling operation being an operation to repeat an inquiry to the designated memory element until detecting that a status of the designated memory element is changed from a busy status to a ready status, the busy status being a status in which the designated memory element cannot receive, from the memory controller, any of commands for instructing input/output of data or execution of an internal operation, the ready status being a status in which the designated memory element can receive, from the memory controller, a command instructing the input/output of data or execution of the internal operation,
the inquiry includes:
issuing, via one of the one or more channels, a status read command to the designated memory element;
receiving, via the one of the one or more channels, status information from the designated memory element; and
determining whether the status of the designated memory elements is the busy status or the ready status, based on the received status information;
wherein
the first number of memory elements include at least a first memory element and a second memory element,
the second number of polling circuits include at least a first polling circuit and a second polling circuit, and
the first processor is configure to perform processing while the first polling circuit is executing the polling operation on the first element, the processing including:
issuing a first command to instruct the second memory element to execute an internal operation;
selecting the second polling circuit that is not executing the polling operation; and
designated the second memory element for the second polling circuit, and causing the second polling circuit to execute the polling operation on the designated second memory element.