US 12,443,540 B1
Virtual memory circuit with virtual address encoding
Muhamed Fawzi Mudawar, Dhahran (SA)
Assigned to KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS, Dhahran (SA)
Filed by KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS, Dhahran (SA)
Filed on Jun. 20, 2025, as Appl. No. 19/244,257.
Application 19/244,257 is a continuation of application No. 18/347,650, filed on Jul. 6, 2023.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 12/1009 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 12/1027 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A virtual memory circuitry that encodes a virtual address (VA) in a VA memory for four different page sizes in a main memory, with a virtual page number encoded in settable bitfields of the VA,
wherein page size PS is implicit in the VA according to which bits in the VA are zeros,
multiple page table registers for separate address spaces;
a 16 MB one-level page table having 221×8-byte entries indexed by a 21-bit virtual page number (VPN21), and
the virtual memory circuitry selecting, using an address space (AS) field, a page table register among the page table registers, which stores a physical page table number and its size.