US 12,443,538 B2
Cache systems
Olof Henrik Uhrenholt, Lund (SE); Edvard Fielding, Trondheim (NO); and Ole Henrik Jahren, Trondheim (NO)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Dec. 16, 2022, as Appl. No. 18/067,180.
Claims priority of application No. 2118624 (GB), filed on Dec. 21, 2021; application No. 2118626 (GB), filed on Dec. 21, 2021; and application No. 2118631 (GB), filed on Dec. 21, 2021.
Prior Publication US 2023/0195638 A1, Jun. 22, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 12/0808 (2016.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01); G06F 12/0891 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0808 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0824 (2013.01); G06F 2212/1016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a cache system that comprises plural coherent caches operable to cache data stored in memory for a processor;
the method comprising:
maintaining link information indicating, for a cache entry in a cache of the plural coherent caches that caches payload data that is associated with header data that is cached by another cache entry in the same cache, a link between the cache entry in the cache that caches the payload data and the another cache entry in the same cache that caches the header data; and
maintaining cache coherence for the plural coherent caches using the link information by, in response to invalidation of a cache entry in the cache that caches header data:
using the link information to identify any cache entries in the same cache that cache payload data that is associated with the header data; and
invalidating the identified cache entries.