US 12,443,535 B2
Joint scheduler for high bandwidth multi-shot prefetching
Yiftach Gilad, Givat Ada (IL); and Liron Zur, Haifa (IL)
Assigned to Next Silicon Ltd, Givatayim (IL)
Filed by Next Silicon Ltd, Givatayim (IL)
Filed on Jul. 12, 2024, as Appl. No. 18/770,690.
Application 18/770,690 is a continuation of application No. 18/537,927, filed on Dec. 13, 2023, granted, now 12,038,843.
Prior Publication US 2025/0199959 A1, Jun. 19, 2025
Int. Cl. G06F 12/08 (2016.01); G06F 12/0862 (2016.01); G06F 12/0897 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 12/0897 (2013.01); G06F 2212/602 (2013.01); G06F 2212/6024 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A joint scheduler, comprising:
a joint scheduler circuit adapted for dispatching prefetch and demand accesses of data relating to a plurality of instructions loaded in an execution pipeline of at least one processing circuit, each prefetch access comprises checking whether a respective data is cached in one of a plurality of cache entries of at least one cache, each demand access comprises accessing a respective data;
the joint scheduler circuit is adapted to:
responsive to each missed prefetch access dispatched for a respective data relating to a respective one of the plurality of instructions, initiate a read cycle for loading the respective data from next level memory and cache it in the at least one cache; and
responsive to successful completion of a respective read cycle initiated for loading a respective data from the next level memory and caching it in the at least one cache following a respective missed prefetch access, associate the respective instruction with a valid indication and a pointer to the respective cache entry storing the cached respective data.