US 12,443,528 B2
Memory management circuit, electronic device and memory management method
Ying-Lin Liu, Hsinchu (TW); Chung-Lun Huang, Hsinchu (TW); Shih-Chang Lin, Hsinchu (TW); Yu-Cheng Lin, Hsinchu (TW); and Lin Liu, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Nov. 17, 2023, as Appl. No. 18/512,038.
Prior Publication US 2025/0165401 A1, May 22, 2025
Int. Cl. G06F 12/0804 (2016.01); G06F 12/0873 (2016.01)
CPC G06F 12/0804 (2013.01) [G06F 12/0873 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory management circuit, comprising:
a controller, configured to record first addresses of available storage spaces within a first memory device, and control operations of generating a mapping table in response to a storage request of a computing circuit, wherein the controller comprises:
a searching logic circuit, configured to store the first addresses in a storage device and generate the mapping table, wherein the first addresses are queued with a specific order in the storage device;
wherein when the computing circuit sends the storage request to request for a specific capacity of storage, the searching logic circuit obtains at least one first address of the first addresses queued in the storage device according to the specific order of the first addresses queued in the storage device, to generate the mapping table according to the at least one first address obtained from the storage device; and
an address mapping logic circuit, coupled to the controller, configured to perform an address mapping operation upon the storage request according to the mapping table, to allow the computing circuit to utilize at least a portion of the available storage spaces within the first memory device according to the mapping table;
wherein the storage device is a first in first out (FIFO) storage device comprising a plurality of storage units, the storage units are configured to store the first addresses, respectively, and the searching logic circuit further comprises:
at least one register, configured to store a pointer which indicates a specific storage unit among the storage units;
wherein the storage device outputs the at least one first address starting from the specific storage unit indicated by the pointer, after the storage device outputs the at least one first address, the searching logic circuit updates the pointer to indicate a subsequent storage unit among the storage units according to a number of the at least one first address being output, in order to make the storage device output a subsequent first address of the first addresses starting from the subsequent storage unit when a subsequent capacity of storage is requested, the specific storage unit is an Nth storage unit among the storage units, the number of the at least one first address being output is M, and the subsequent storage unit is an (N+M)th storage unit among the storage units, wherein each of N and M is a positive integer.