| CPC G06F 12/0246 (2013.01) | 20 Claims |

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1. A memory device, comprising:
an array of memory cells, including a plurality of memory cells; wherein a preset number of the memory cells forms a code word; and
a peripheral circuit coupled to the array of memory cells and configured to:
obtain a first state corresponding to at least one of the code words at a target read voltage; wherein the first state includes a state that represents a relationship of size between a number of bits in the at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage and a first preset value; and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage;
read data stored in at least one of the code words at the target read voltage to obtain a first result;
perform a first adjustment to the target read voltage and read data stored in at least one of the code words at an adjusted target read voltage to obtain a second result;
perform a logical operation on the first result and the second result to obtain a third result;
compare the number of bits in the third result that represent flip of bits in the second result relative to the first result and the first preset value to obtain a first state; and
determine a valley voltage in accordance with a variation trend of the relationship of size between the number of flipped bits and the first preset value indicated by the first state; wherein the valley voltage is a read voltage for performing a read operation on the at least one of the code words.
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