US 12,443,520 B2
Dynamic word line allocation in memory systems
Tarun Singh Yadav, Boise, ID (US); Scott Anthony Stoller, Boise, ID (US); Pitamber Shukla, San Jose, CA (US); Fulvio Rori, Boise, ID (US); Attila A. Herrera, Boise, ID (US); and Justin Bates, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 19, 2024, as Appl. No. 18/417,517.
Claims priority of provisional application 63/443,841, filed on Feb. 7, 2023.
Claims priority of provisional application 63/440,834, filed on Jan. 24, 2023.
Prior Publication US 2024/0249789 A1, Jul. 25, 2024
Int. Cl. G06F 12/02 (2006.01); G11C 29/12 (2006.01)
CPC G06F 12/0246 (2013.01) [G11C 29/1201 (2013.01); G06F 2212/1036 (2013.01); G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a set of memory components of a memory sub-system; and
a processing device operatively coupled to the set of memory components, the processing device being configured to perform operations comprising:
accessing reliability data of a set of main word lines (WLs) of a block of the set of memory components;
determining that one or more WLs of the set of main WLs of the block are associated with respective reliability data that transgress a threshold;
in response to determining that the one or more WLs are associated with the respective reliability data that transgress the threshold, replacing the one or more WLs of the set of main WLs of the block with one or more dummy WLs; and
alternatively cycling between programming data to the block using the one or more WLs that are associated with respective reliability data that transgress the threshold and the one or more dummy WLs.