US 12,443,486 B2
Evaluation of memory device health monitoring logic
Scott E. Schaefer, Boise, ID (US); Aaron P. Boehm, Boise, ID (US); Scott D. Van De Graaff, Boise, ID (US); Mark D. Ingram, Boise, ID (US); and Todd Jackson Plum, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 31, 2024, as Appl. No. 18/680,470.
Application 18/680,470 is a continuation of application No. 17/807,813, filed on Jun. 20, 2022, granted, now 12,038,806.
Claims priority of provisional application 63/365,733, filed on Jun. 2, 2022.
Prior Publication US 2024/0320093 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 9/30 (2018.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 9/30189 (2013.01); G06F 11/0772 (2013.01); G06F 11/3051 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving one or more indications to evaluate a set of internal monitors for health monitoring of a memory device according to both a first configuration of the set of internal monitors and a second configuration of the set of internal monitors;
activating a first subset of internal monitors of the set of internal monitors according to the first configuration of the set of internal monitors, wherein activating the first subset of internal monitors comprises activating one or more first switching components configured to couple the first subset of internal monitors with aggregation circuitry; and
activating a second subset of internal monitors of the set of internal monitors according to the second configuration of the set of internal monitors, wherein activating the second subset of internal monitors comprises activating one or more second switching components configured to couple the second subset of internal monitors with the aggregation circuitry.