US 12,443,482 B2
Memory including ECC engine
Jae Hun Lee, Gyeonggi-do (KR); Sun Ho Kim, Gyeonggi-do (KR); Yong Mi Kim, Gyeonggi-do (KR); and Sang Uhn Cha, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 23, 2024, as Appl. No. 18/585,336.
Claims priority of application No. 10-2023-0168735 (KR), filed on Nov. 29, 2023.
Prior Publication US 2025/0173215 A1, May 29, 2025
Int. Cl. G06F 11/08 (2006.01)
CPC G06F 11/08 (2013.01) 15 Claims
OG exemplary drawing
 
1. A memory comprising:
a memory core;
a first ECC engine configured to correct an error having a first pattern, occurring in read data read from the memory core;
a second ECC engine configured to correct an error having a second pattern, occurring in the read data read from the memory core, wherein one of the first ECC engine and the second ECC engine is selectively activated based on an address used to access the memory core; and
a data swap circuit configured to change an arrangement of data transmitted between a selected ECC engine and the memory core according to the address.