US 12,443,477 B2
Method and apparatus for high-performance page-fault handling for multi-tenant scalable accelerators
Utkarsh Y. Kakaiya, Folsom, CA (US); Philip Lantz, Cornelius, OR (US); Sanjay Kumar, Hillsboro, OR (US); Rajesh Sankaran, Portland, OR (US); Narayan Ranganathan, Banglore (IN); Saurabh Gayen, Portland, OR (US); Dhananjay Joshi, Portland, OR (US); and Nikhil P. Rao, Bengaluru (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/560,170.
Claims priority of provisional application 63/226,159, filed on Jul. 27, 2021.
Prior Publication US 2023/0042934 A1, Feb. 9, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/079 (2013.01) [G06F 11/0775 (2013.01); G06F 11/0784 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; and
fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, page fault handling modes for the plurality of work queues including a first page fault handling mode and a second page fault handling mode, wherein upon a page fault occurring on an address associated with a completion record buffer, information associated with the page fault is submitted to an event log but not the completion record buffer.