| CPC G06F 9/544 (2013.01) [G06F 8/453 (2013.01); G06F 9/5016 (2013.01); G06F 9/5038 (2013.01); G06F 2209/507 (2013.01)] | 30 Claims |
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1. A method, the method comprising:
allocating, by a computer-implemented Buffer-Pipeline Manager (BPM), responsive to a first interface of a Pipeline Programming Interface (PPI) of a Buffer Pipelined Application computing System (BPAS), based on execution parameters associated with the BPAS executing a pipelined application, a plurality of pipeline buffers, the BPM included in the BPAS, the pipelined application comprising a plurality of application execution stages, the BPAS comprising a plurality of stage processors to execute corresponding execution stages among plurality of application execution stages, the plurality of pipeline buffers included in at least one physical memory of the BPAS;
configuring, by the BPM, access to a first buffer, among the plurality of pipeline buffers, by a first stage processor among the plurality of stage processors, the first buffer included in a first region of a first physical memory, the first physical memory among the at least one physical memory of the BPAS, the first stage processor to execute a first execution stage, among the plurality of application execution stages of the pipelined application, utilizing the first buffer;
initiating, by the BPM, responsive to the configuring the access to the first buffer by the first stage processor, operations of the first stage processor utilizing the first buffer;
determining, by the BPM, a first buffer ready status associated with a processing operation of the first stage processor on data included in the first buffer, the first data ready status corresponding to second stage input data ready for processing by a second stage processor, the second stage input data comprising data output by an operation of the first stage processor, the second stage processor to execute a second execution stage, among the plurality of application execution stages, to process the second stage input data;
transferring, by the BPM in response to the first buffer ready status, the first buffer to the second stage processor for processing, by the second stage processor, the second stage input data; and,
configuring, by the BPM, responsive to the transferring the first buffer, access by the second stage processor to a second buffer among the plurality of pipeline buffers, the second buffer including the second stage input data, the second buffer included in a second region of a second physical memory, the second memory among the at least one physical memory of the BPAS.
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