US 12,443,461 B2
Circuit and method of handling load balance
Wun-Ci Su, HsinChu (TW); Jhe-Yi Lin, HsinChu (TW); and Yu-Jhao Yang, HsinChu (TW)
Assigned to Realtek Semiconductor Corp., HsinChu (TW)
Filed by Realtek Semiconductor Corp., HsinChu (TW)
Filed on May 3, 2023, as Appl. No. 18/143,048.
Claims priority of application No. 111116770 (TW), filed on May 4, 2022.
Prior Publication US 2023/0359502 A1, Nov. 9, 2023
Int. Cl. G06F 9/50 (2006.01)
CPC G06F 9/505 (2013.01) 10 Claims
OG exemplary drawing
 
1. A load balance circuit, comprising:
a storing circuit, for storing at least one first user field number corresponding to at least one first node in a minimum full binary tree, wherein at least one first resource unit (RU) corresponding to the at least one first node is smaller than or equal to an RU size;
a user field number generation circuit, coupled to the storing circuit, for generating at least one third user field number according to at least one second user field number corresponding to at least one second node in the minimum full binary tree, and generating at least one second weight according to at least one first weight corresponding to the at least one second node, wherein at least one second RU corresponding to the at least one second node is greater than the RU size; and
a load balance calculation circuit, coupled to the user field number generation circuit, for generating a plurality of first user field numbers corresponding to a plurality of content channels according to the at least one first user field number, the at least one third user field number, the at least one second weight, a load balance function and the at least one first weight.