US 12,443,458 B2
Efficient accelerator offload in multi-accelerator framework
Akhilesh S. Thyagaturu, Tempe, AZ (US); Mohit Kumar Garg, Hisar (IN); and Vinodh Gopal, Westborough, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 17, 2021, as Appl. No. 17/529,149.
Prior Publication US 2022/0075655 A1, Mar. 10, 2022
Int. Cl. G06F 9/50 (2006.01)
CPC G06F 9/505 (2013.01) [G06F 9/5033 (2013.01); G06F 9/5044 (2013.01); G06F 9/5088 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method implemented in a compute platform including a plurality of processor cores and a plurality of accelerator devices, comprising:
executing an application on a first core;
offloading a first offloaded portion of a workload for the application to a first accelerator device;
moving execution of the application from the first core to a second core;
selecting a second accelerator device to be used based on core-to-accelerator cost information for the second core; and
offloading the first offloaded portion of the workload to the second accelerator device,
wherein the core-to-accelerator cost information for the second core is based, at least on part, on latencies projected for interconnect paths between core-accelerator pairs including the second core and accelerators among the plurality of accelerators.