US 12,443,447 B2
Memory sharing for machine learning processing
Mihir Narendra Mody, Bengaluru (IN); Kedar Satish Chitnis, Bengaluru (IN); Kumar Desappan, Bengaluru (IN); David Smith, Allen, TX (US); Pramod Kumar Swami, Bengaluru (IN); and Shyam Jagannathan, Bengaluru (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on May 28, 2024, as Appl. No. 18/675,294.
Application 18/675,294 is a continuation of application No. 17/378,841, filed on Jul. 19, 2021, granted, now 11,995,472.
Prior Publication US 2024/0320045 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/50 (2006.01); G06F 9/455 (2018.01); G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06N 3/02 (2006.01); G06N 3/10 (2006.01); G06N 20/00 (2019.01)
CPC G06F 9/5016 (2013.01) [G06F 9/5077 (2013.01); G06F 12/00 (2013.01); G06F 12/0223 (2013.01); G06F 2009/45583 (2013.01); G06F 9/50 (2013.01); G06F 9/5022 (2013.01); G06N 3/02 (2013.01); G06N 3/10 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first processing core configured to perform a first algorithm;
a second processing core;
a first memory coupled to the first processing core and configurable to be allocated to the first algorithm; and
a second memory coupled to the first processing core and the second processing core, wherein:
the second memory is configurable to be shared between the first processing core and the second processing core; and
the first processing core is configured to perform the first algorithm using the first memory and the second memory.