| CPC G06F 9/3887 (2013.01) [G06F 9/4812 (2013.01); G06F 9/526 (2013.01)] | 6 Claims |

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1. A memory device comprising:
a memory region;
a plurality of subcores; and
a main core configured to control a subcore of the plurality of subcores to perform a preprocessing task in response to a preprocessing command and control one or more subcores of the plurality of subcores to perform one or more main tasks in response to an operation command subsequent to the preprocessing command,
wherein the preprocessing task includes a sub-operation of setting a peripheral circuit coupled to a target location in the memory region before accessing the target location, and
wherein the one or more main tasks includes a sub-operation of accessing the target location.
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