US 12,443,410 B2
Decoding method of simultaneously multi-threading processor, processor, and chip
Zehan Cui, Tianjin (CN)
Assigned to HYGON INFORMATION TECHNOLOGY CO., LTD., (CN)
Appl. No. 18/833,997
Filed by HYGON INFORMATION TECHNOLOGY CO., LTD., Tianjin (CN)
PCT Filed Sep. 13, 2023, PCT No. PCT/CN2023/118573
§ 371(c)(1), (2) Date Jul. 29, 2024,
PCT Pub. No. WO2024/093541, PCT Pub. Date May 10, 2024.
Claims priority of application No. 202211348787.1 (CN), filed on Oct. 31, 2022.
Prior Publication US 2025/0123845 A1, Apr. 17, 2025
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3814 (2013.01) [G06F 9/30145 (2013.01); G06F 9/3818 (2013.01); G06F 9/3822 (2013.01); G06F 9/3851 (2013.01); G06F 9/3836 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A decoding method of a simultaneously multi-threading processor, comprising:
fetching an instruction stream according to an instruction fetching request;
segmenting the instruction stream which is fetched in response to the simultaneously multi-threading processor being in a single-threaded mode;
allocating the instruction stream which is segmented to multiple target instruction queues by using an instruction at a segmentation position as a boundary of switching instruction queues, wherein the multiple target instruction queues comprise an instruction queue corresponding to an active thread and one or more instruction queues corresponding to one or more inactive threads; and
decoding instructions in the multiple target instruction queues by using multiple decoder groups, so as to obtain micro-ops decoded by respective decoder groups, wherein one decoder group decodes instructions in one or more corresponding target instruction queues, and in the single-threaded mode, one decoder group corresponds to at least one target instruction queue.