| CPC G06F 9/30145 (2013.01) [G06F 7/49 (2013.01); G06F 7/722 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); H04L 9/008 (2013.01); H04L 9/30 (2013.01)] | 15 Claims |

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13. A processor comprising:
first circuitry to decode an instruction, the instruction to indicate a first source packed data operand and a second source operand, the first source packed data operand to have a first plurality of integer data elements and the second source operand to have an integer data element; and
second circuitry including a processing resource to perform operations corresponding to the instruction, including to:
determine whether each integer data element of the first plurality of integer data elements is greater than or equal to the integer data element of the second source operand;
for each integer data element of the first plurality of integer data elements that is greater than or equal to the integer data element of the second source operand, output a corresponding result data element in a result packed data that is equal to the integer data element of the first plurality of integer data elements minus the integer data element of the second source operand; and
for each integer data element of the first plurality of integer data elements that is not greater than or equal to the integer data element of the second source operand, output the corresponding integer data element of the first plurality of integer data elements as a corresponding result data element in the result packed data.
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