US 12,443,372 B2
Memory system and method of controlling memory chips
Konosuke Watanabe, Kawasaki (JP); Shinji Yonezawa, Machida (JP); Eiji Sukigara, Kawaguchi (JP); Mitsusato Hara, Sagamihara (JP); Haruka Mori, Kawasaki (JP); and Hajime Yamazaki, Kawasaki (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 4, 2024, as Appl. No. 18/594,070.
Claims priority of application No. 2023-033708 (JP), filed on Mar. 6, 2023.
Prior Publication US 2024/0302997 A1, Sep. 12, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0688 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory system comprising:
a random access memory;
a plurality of nonvolatile memory chips, each of the plurality of nonvolatile memory chips including a page buffer and a memory cell array, the plurality of nonvolatile memory chips including at least a first nonvolatile memory chip and a second nonvolatile memory chip; and
a controller configured to:
determine, for each of the plurality of nonvolatile memory chips, whether or not data to be written next thereto is being stored in the random access memory;
determine, of the plurality of nonvolatile memory chips, a nonvolatile memory (A) in which data is being written from the page buffer to the memory cell array and (B) for which the random access memory is storing the data to be written next, as being in a busy state; and
when one or more requests issued by a host are stored in at least one queue of the host, each of the one or more requests designating one of the nonvolatile memory chips as a target on which a corresponding process is to be executed,
identify, from the one or more requests, a first request for the first nonvolatile memory chip that is not in the busy state,
execute a process in accordance with the identified first request,
fetch a second request from the queue, and
in response to determining that the second nonvolatile memory chip, which is a target of the second request, is in the busy state, suspend execution of a process in accordance with the fetched second request until the second nonvolatile memory chip becomes not in the busy state.