| CPC G06F 3/0659 (2013.01) [G06F 3/0607 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
|
1. A device comprising:
a processor; a memory array comprising a plurality of memory devices; and
an accelerated processing logic configured to:
receive incoming commands;
parse the received incoming commands;
pass one or more parsed commands to a parallel accelerated processing pipeline, wherein the parallel accelerated processing pipeline comprising a first accelerated processing memory in a front-end and flash translation layer and a second accelerated processing memory in a physical storage layer;
perform, within the parallel accelerated processing pipeline, one or more verifications on the parsed command, to determine its eligibility for prioritized die-specific processing, wherein the one or more verifications comprise at least determining if data associated with the parsed command is accessible from one or more cache memories;
determine a die associated with the parsed command;
add, upon passing the one or more verifications, the parsed command into a priority queue among the one or more priority queues wherein the priority queue is associated with the determined die,
arbitrate the parsed command against one or more non-priority queues; and process the parsed command in the priority queue before commands within a non-priority queue.
|