US 12,443,367 B2
Perfect row hammer tracking with multiple count increments
Bill Nale, Livermore, CA (US); and Kuljit S. Bains, Olympia, WA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,598.
Prior Publication US 2022/0121398 A1, Apr. 21, 2022
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01); G11C 11/406 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 11/406 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
command logic to generate access commands to N different row addresses of a memory device that internally increments a row address activate count, and to generate a subsequent access command for a first row address of the memory device; and
circuitry to determine whether the first row address is one of the N different row addresses;
wherein if the first row address is not one of the N different row addresses, the command logic is to generate an indication command to send to the memory device to trigger the memory device to internally increment the activate count by M, wherein M is an integer greater than one; and
wherein if the first row address is one of the N different row addresses, the command logic is to generate an indication command to send to the memory device to trigger the memory device to internally not increment the activate count.