US 12,443,363 B2
High bandwidth extended memory in a parallel processing system
Hemayet Hossain, San Jose, CA (US); Steven E. Molnar, Chapel Hill, NC (US); Jonathon Stuart Ramsay Evans, Santa Clara, CA (US); Wishwesh Anil Gandhi, Sunnyvale, CA (US); Lacky V. Shah, Los Altos Hills, CA (US); Vyas Venkataraman, Sharon, MA (US); Mark Hairgrove, San Jose, CA (US); Geoffrey Gerfin, San Jose, CA (US); Jeffrey M. Smith, Barrington, RI (US); Terje Bergstrom, San Jose, CA (US); Vikram Sethi, Austin, TX (US); and Piyush Patel, Cary, NC (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Mar. 18, 2022, as Appl. No. 17/698,409.
Prior Publication US 2023/0315328 A1, Oct. 5, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method for accessing extended memory allocated within a system memory of a central processing unit, the method comprising:
receiving, at a first parallel processor that is coupled to the central processing unit, a first memory access from a second parallel processor;
determining that the first memory access is directed towards the extended memory allocated within the system memory of the central processing unit; and
transmitting the first memory access from the first parallel processor to a memory controller that is coupled to the central processing unit for processing,
wherein the extended memory is pinned in the system memory of the central processing unit for exclusive access by the second parallel processor.