US 12,443,362 B2
Technologies for burst memory write operations
Setul M. Shah, Folsom, CA (US); and Rajesh Sundaram, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 24, 2021, as Appl. No. 17/357,840.
Prior Publication US 2022/0413740 A1, Dec. 29, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A phase-change-based memory die comprising:
a plurality of partitions; and
a chip controller, the chip controller to:
receive a first memory write operation at a first time;
receive a second memory write operation at a second time; and
receive a memory read operation after receipt of the second memory write operation,
wherein the phase-change-based memory die has a minimum average time period between write operations,
wherein a time between the first time and the second time is less than the minimum average time period between write operations,
wherein the chip controller is further to:
perform the first memory write operation at a third time;
perform the second memory write operation at a fourth time, wherein a time between the third time and the fourth time is at least the minimum average time period between write operations; and
perform the memory read operation before performance of the second memory write operation.