US 12,443,357 B2
Memory system and method
Yuji Takahashi, Tokyo (JP); and Hirokazu Hanaki, Kanagawa (JP)
Assigned to Sony Group Corporation, Tokyo (JP)
Appl. No. 18/293,063
Filed by Sony Group Corporation, Tokyo (JP)
PCT Filed Mar. 8, 2022, PCT No. PCT/JP2022/009933
§ 371(c)(1), (2) Date Jan. 29, 2024,
PCT Pub. No. WO2023/021751, PCT Pub. Date Feb. 23, 2023.
Claims priority of application No. 2021-134699 (JP), filed on Aug. 20, 2021.
Prior Publication US 2024/0329869 A1, Oct. 3, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 13/28 (2006.01)
CPC G06F 3/0644 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0673 (2013.01); G06F 13/28 (2013.01); G06F 2206/1004 (2013.01); G06F 2213/28 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory including a plurality of pages on each of which data can be arranged;
a defragmenting device that rearranges the data arranged on the plurality of pages, wherein
the memory includes a plurality of tiles each including one or more pages,
each of the plurality of tiles is configured to be capable of transitioning among a plurality of states in which power consumption suppression rates are different,
the plurality of states include a low power consumption state different from a power-off state, and
the defragmenting device rearranges the data such that a tile in which high access frequency data are collected and a tile in which low access frequency data are collected are present, and the defragmenting device rearranges the data based on a comparison result of an access frequency maximum value of one tile among tiles adjacent to each other in a number management and an access frequency minimum value of an other tile.